IP Catalog

A crossbar with proofs where it counts: round-robin fairness bound and end-to-end correctness.

7

MODULES

fairness + e2e

FORMAL

scoreboarded

RANDOMIZED

31 streaming building blocks at full coverage — with four upstream defects found and fixed on the way.

31 / 31 verified

MODULES

28

SUITES

345

TESTS

55 AXI4 infrastructure modules — crossbar, DMA, RAMs, adapters — 55/55 verified, zero RTL defects found.

55 / 55 verified

MODULES

500

TESTS

≈143 MHz

FMAX (XBAR 4×4)

AXI4-Lite ↔ APB / Wishbone converters — both directions, each with an unconditional formal proof of far-side protocol legality.

4

BRIDGES

2 proofs

FORMAL

23–48 LUT

COST

Classic Wishbone building blocks — RAMs, bridges, CDC, mux, arbiter, width adapter, stream master — 8/8 verified.

8 / 8 verified

MODULES

74

TESTS

8 / 8

MUTANTS CAUGHT

An embedded logic analyzer you can leave in the design — arm, trigger, capture, read back over AXI4-Lite.

3

MODULES

capture proofs

FORMAL

Arty A7-100T

HIL

A JTAG TAP to AXI bridge with a formally proven state machine and CDC handshake.

7

MODULES

TAP + CDC proofs

FORMAL

report_cdc clean

CDC

A CSR-driven UART whose FIFO and frame shape are proofs, not hopes — echo-tested on real silicon.

9

MODULES

98.7%

LINE COVERAGE

Arty echo demo

HIL

Master and slave I2C with AXI4-Lite and Wishbone faces — every module exercised, 9/9.

9 / 9 verified

MODULES

20

TESTS

8

SUITES

AXI4-Lite GPIO — up to 32 pins, atomic set/clear/toggle, debounce, per-pin edge/level interrupts — with a formal proof of the IRQ engine.

1–32

PINS

1 proof

FORMAL

≈211 MHz

FMAX

AXI4-Lite timer/counter with PWM — prescaled period (auto-reload / one-shot), N channels, wrap & compare-match interrupts — formally proven counter + PWM.

4 (parametric)

PWM CH

1 proof

FORMAL

≈172 MHz

FMAX

FIPS-197 AES-128/192/256 — ECB, CBC, CTR, GCM — with formal S-box and datapath proofs.

34

MODULES

2,526

KAT VECTORS

3 proofs

FORMAL

RFC 8439 AEAD with XChaCha extension — tag-before-release discipline, formally proven rounds.

14

MODULES

3 proofs

FORMAL

RFC 8439

VECTORS

Pipelined CORDIC for sin/cos/atan/magnitude — every stage formally proven, error-bounded.

11

MODULES

6

CONFIGS PROVEN

105/105 lines

COVERAGE

10/100, 1G and 10G MACs with PTP timestamping — 69/74 modules verified, six upstream defects fixed.

69 / 74 verified

MODULES

51

SUITES

296

TESTS

Hardware IPv4 + UDP above the MAC — verified module by module, in the open, all 24 covered.

24

MODULES

24 / 24

VERIFIED

138

TESTS