Wishbone Infrastructure

The infrastructure layer for classic (non-pipelined) Wishbone: single- and true-dual-port RAMs, a register slice, a clock-domain-crossing bridge, a 2-slave address-decoding mux, a 2-master arbiter, an 8/16/32/64-bit width adapter, and a byte-stream framed Wishbone master for driving a bus over UART or UDP.

All 8 modules verified with independent oracles — dict-backed byte/word memory models behind every bridge, struct-packed frames for the stream master — across 74 tests, then mutation-checked (8 targeted mutants, all caught). The width adapter is exercised across five master/slave ratios. Two behaviours worth knowing before you integrate are documented, not buried: the CDC bridge needs the slave cycle to outlast one master clock, and the stream master's write response completes before the data reaches the bus.