AXI4 Library

Full-fat AXI4 infrastructure: crossbars and interconnects, DMA and CDMA with descriptor engines, block RAMs, width/burst adapters, register slices, virtual FIFOs. All 55 modules verified — 26 with their own suites, the rest reached transitively and the datasheet is honest about the difference.

A distinction worth advertising: across the entire verification campaign, no RTL defect has ever been found in this library. The five suites that were failing when we adopted it were all testbench-layer API drift — and the datasheet documents each one.