Ethernet MAC

A complete layer-2 stack: MACs from 10/100 MII through 1G GMII/RGMII to 10G XGMII, 10GBASE-R PCS, PTP/1588 time distribution, pause/PFC flow control, ARP, and FCS engines at both 8-bit and 64-bit widths. Split deliberately from the IP/UDP layers — a MAC is independently useful, and the dependency runs one way.

The verification campaign found six real defects in modules upstream ships untested — every one the same shape: logic that handles the general case and silently breaks the degenerate one. Single-beat frames, single-word tags, non-contiguous keeps. They're fixed, and each deviation is documented in the RTL at the point of change.

Honesty note you won't often see on an IP page: the 10G MAC reaches ~118 MHz on an Artix-7 -1 against the 156.25 MHz line rate — so no 10G hardware claim is made on that part. The five unverified modules are vendor-primitive IO cells that Icarus can only simulate behaviourally; counting them as 'verified' would claim something simulation cannot show.