IPWEAVE

In active development — new modules verified weekly

Silicon IP you can actually trust, woven into your SoC by one command.

IPWEAVE is a free catalogue of SystemVerilog IP — interconnect, Ethernet, crypto, peripherals — where every module is verified, every claim is reproducible from the repo, and every core ships as IEEE 1685 IP-XACT that our elaborator turns into an integrated design.

Browse the catalogue Read the docs
16
IP families
213
IP-XACT components
1,235+
regression tests, all green
21
formal proof groups

One quality bar. No exceptions.

Open-source RTL is a minefield of untested modules and optimistic READMEs. We adopted a different standard and applied it to every core in the catalogue — our own and the ones we imported.

Verification, reproducible

Every module exercised; every number on a datasheet regenerable from the repo. Independent oracles, degenerate-case tests, mutation-tested suites. Our campaign has found and fixed ten real defects upstream ships to everyone.

IP-XACT, usable

All 213 components are IEEE 1685-2014 packages with interfaces, parameters and register maps — not tarballs. The weft elaborator consumes them directly: name VLNVs, get an integrated design.

Datasheets, honest

Structurally identical across all IPs, with limitations recorded instead of hidden. When our 10G MAC misses timing on an Artix-7, the datasheet says so. When a stack isn't verified yet, it says that too.

From catalogue to integrated RTL in three steps

01

Browse

Pick cores from the catalogue — interfaces, parameters and register maps are first-class data, not PDF archaeology.

02

Describe

Write a small design file naming component VLNVs and connections. No vendor GUI, no project files — plain YAML you can diff and review.

03

Weave

The platform elaborates your design and returns the integrated result with full elaboration reporting — warnings, ports, instances.

top: my_soc
instances:
  dma:  { vlnv: "ipweave:ip:axi_dma:1.0" }
  uart: { vlnv: "ipweave:ip:uart_axil:1.0" }
  bar:  { vlnv: "ipweave:ip:xbar_axil:1.0" }

$ curl -X POST https://api.ipweave.com/weave  →  ok: true · 3 components · 0 errors

In the catalogue

Free to use through the platform. Verified before you ever see them.

AXI4 Library

v1.2

55 AXI4 infrastructure modules — crossbar, DMA, RAMs, adapters — 55/55 verified, zero RTL defects found.

55 / 55 verified modules

Ethernet MAC

v1.1

10/100, 1G and 10G MACs with PTP timestamping — 69/74 modules verified, six upstream defects fixed.

69 / 74 verified modules

AES

v1.0

FIPS-197 AES-128/192/256 — ECB, CBC, CTR, GCM — with formal S-box and datapath proofs.

34 modules

UART

v1.0

A CSR-driven UART whose FIFO and frame shape are proofs, not hopes — echo-tested on real silicon.

9 modules

Need something the catalogue doesn't have?

The same team that verifies this catalogue takes on custom work: bespoke IP development, integration of catalogue cores into your SoC, verification of RTL you already have, and premium support with guaranteed response times. If it should exist and hold the same bar, we can build it.

Custom IP & services

Keep it free. Sponsor the catalogue.

Every core here is free because verification effort is funded by the people who benefit from it existing. Sponsors get their name on the work, early input on the roadmap, and a catalogue their own teams draw from — verified once, used everywhere.

Become a sponsor