Custom IP & services
The catalogue is free and stays free. Around it, we offer paid engineering for teams that need more: new cores, integration work, verification muscle, or guaranteed support. Same team, same standard, your requirements.
Custom IP development
A core the catalogue doesn't have, or a variant of one that does — different bus, different width, different feature set. Built in SystemVerilog to the same standard as everything here: native testbenches, formal proofs where they earn their keep, an honest datasheet, IP-XACT packaging.
Fixed-scope quotes. You get the RTL, the verification collateral, and the reproduction commands — not just a netlist.
Integration engineering
We wire catalogue cores into your SoC: interconnect topology, clock/reset architecture, register map consolidation, and the weave configuration that reproduces the whole assembly on demand.
Ideal when your team owns the application logic and wants the infrastructure handled.
Verification of your RTL
Bring us a core you already have. We apply the catalogue's methodology to it — independent oracles, degenerate-case suites, mutation testing, formal where it fits — and hand back suites, findings, and a datasheet-grade report.
Our campaign found ten silent defects in widely-used open cores. Yours deserve the same scrutiny before tape-out.
Premium support
Guaranteed response times on catalogue IP, priority fixes, direct access to the engineers who wrote the verification, and early access to roadmap cores.
For teams shipping products on top of the catalogue.
Tell us the problem
A short email is enough — target process or FPGA, interfaces, constraints, timeline.
Get a scoped proposal
Fixed scope and deliverables, including the verification plan — you'll know what 'done' means before we start.
Receive reproducible work
RTL + suites + datasheet + IP-XACT. Every claim regenerable from the deliverable, like the catalogue itself.
Start the conversation
No forms with twelve required fields. Write to us, we answer.