AES

A complete AES implementation: all three key sizes, the four modes that matter (ECB, CBC, CTR, GCM), and an AXI4-Lite control plane with streaming data. Built as SystemVerilog from the first line — no converted legacy RTL.

Verification is the point. The core is checked bit-exact against NIST CAVP known-answer vectors (2,526 of them, plus Monte-Carlo chaining), the S-box composite-field implementation is formally proven equivalent to the lookup table, and the round transforms carry their own equivalence proofs. Gate-level simulation with SDF back-annotation closes the loop against synthesized netlists.