Timer / PWM

A general-purpose timer/counter with pulse-width modulation on an AXI4-Lite control plane: a prescaled counter with a programmable period (continuous auto-reload or one-shot), NUM_PWM PWM channels each with its own compare and polarity, and wrap / compare-match interrupts. Written as SystemVerilog from the first line; no asynchronous inputs, so no vendor-specific cells.

The counter and PWM logic — where an off-by-one on the period or a slip in the duty comparison would hide — are formally proven (SymbiYosys, unbounded): the counter never exceeds its reload, a wrap returns it to zero, one-shot stop is exactly wrap-in-one-shot, and each PWM output equals its specified function of the count and compare. Characterized out-of-context on Artix-7 (399 LUT / 344 FF, ≈172 MHz) and validated on an Arty A7-100T with a breathing-LED PWM demo.