I2C

The proven verilog-i2c core family, converted to clean SystemVerilog and brought to full verification coverage on the platform: master (AXI4-Lite and Wishbone control), slave, slave-to-AXI4-Lite bridge, single-register slave, and the init sequencer. Every one of the nine RTL modules is exercised by a suite checked against an independent BFM model.

Coverage is functional, not just structural — and its limits are documented: clock stretching, multi-master arbitration loss and bus-error recovery are not directly stimulated, and the datasheet says so.