GPIO

A general-purpose I/O controller on an AXI4-Lite control plane: up to 32 pins, each independently input or output, with atomic output set/clear/toggle, metastability-synchronized inputs behind an optional two-sample debounce filter, and a per-pin edge/level interrupt controller. Written as SystemVerilog from the first line.

The interrupt-condition engine — where edge/level detection and polarity live, and where a sign or priority slip would hide — is formally proven equal to its specification (SymbiYosys, unbounded). The rest is covered by a self-checking Verilator testbench, characterized out-of-context on Artix-7 (356 LUT / 498 FF, ≈211 MHz), and validated on an Arty A7-100T. Pads are exposed as value/output-enable/input buses so you place the tri-state IO buffer at the boundary; the only vendor-aware cell is the input synchronizer.