ILA
v1.0PRODUCTIONAn embedded logic analyzer you can leave in the design — arm, trigger, capture, read back over AXI4-Lite.
On-chip visibility without vendor lock-in: a compact integrated logic analyzer with trigger modes, pre-trigger positioning and wrap-around capture, read out over AXI4-Lite or streamed out over AXI4-Stream. Proven on real hardware — the bring-up flow on an Arty A7-100T is part of the repo.
The capture FSM's pointer invariants are formally proven, and the datasheet is explicit about its semantics: the stream tap samples every clock, not only accepted beats — it is a scope, deliberately, and the documentation says so rather than letting you find out.
3
MODULES
capture proofs
FORMAL
Arty A7-100T
HIL
Need this core adapted — different bus, different process, extra features, or verified against your own requirements?
Talk to us about customization